1. Technical Field
The present invention relates to a liquid crystal display device and an electronic apparatus.
2. Related Art
As a liquid crystal display device, a vertical electric field mode liquid crystal display device such as a Twisted Nematic (TN) mode, a Vertical Alignment (VA) mode or a Multi-domain Vertical Alignment (MVA) mode is widely used, but a lateral electric field mode liquid crystal display device including electrodes on one substrate is also known. In the lateral electric field mode liquid crystal display device, the operation principle of an In-Plane Switching (IPS) mode liquid crystal display device will be described with reference to FIGS. 22 and 23 (for example, see JP-A2003-140188).
FIG. 22 is a schematic plan view of one pixel seen through a color filter substrate CF of a known IPS mode liquid crystal display device 150 FIG. 23 is a cross-sectional view taken along line XXIII-XXIII of FIG. 22.
This IPS mode liquid crystal display device 150 includes an array substrate AR and a color filter substrate CF. In the array substrate AR, a plurality of scanning lines 154 and common lines 156 is provided in parallel on the surface of a first transparent substrate 152, and a plurality of signal lines 158 is provided in a direction crossing the scanning lines 154 and the common lines 156. On a central portion of each pixel, for example, a comb teeth-shaped counter electrode (also referred to as a “common electrode”) 160 is provided from each of the common lines 156 in a band shape and a comb teeth-shaped pixel electrode 162 is provided so as to be fitted into the counter electrode 160. The surfaces of the counter electrode 160 and the pixel electrode 162 are, for example, covered by a protective insulating film 164 formed of silicon nitride and an alignment film 166 formed of a polyimide or the like.
In addition, a Thin Film Transistors (TFT) functioning as a switching element is formed at an intersection of each of the scanning lines 154 and each of the signal lines 158. In this TFT, a semiconductor layer 168 is disposed between each of the scanning lines 154 and each of the signal lines 158, a portion of each of the signal lines on the semiconductor layer 168 configures a source electrode S of the TFT, a portion of each of the scanning lines 154 under the semiconductor layer 168 configures a gate electrode G, a conductive layer partially overlapping with a portion of the semiconductor layer 168 configures a drain electrode D, and this drain electrode D is connected to the pixel electrode 162.
In the color filter substrate CF, a color filter layer 172, an overcoat layer 174 and an alignment film 176 are provided on the surface of a second transparent substrate 170. The array substrate AR and the color filter substrate CF face each other such that the pixel electrode 162 and the counter electrode 160 of the array substrate AR and the color filter layer 172 of the color filter substrate CF face each other. Subsequently, liquid crystal LC is filled between the array substrate AR and the color filter substrate CF, and polarization plates 178 and 180 are arranged on the outsides of both substrates such that the polarization directions thereof cross each other, thereby forming the IPS mode liquid crystal device 150.
As shown in FIG. 23, in the IPS mode liquid crystal display device 150, if an electric field is generated between the pixel electrode 162 and the counter electrode 160, the liquid crystal aligned in a horizontal direction turns in the horizontal direction such that the transmission amount of light incident from a backlight can be controlled.
Next, the operation principle of a Fringe Field Switching (FFS) mode liquid crystal display device will be described with reference to FIGS. 24 and 25 (for example, see 2001-56476).
FIG. 24 is a schematic plan view of one pixel seen through a color filter substrate CF of a known FFS mode liquid crystal display device 190. FIG. 25 is a cross-sectional view taken along line XXV-XXV of FIG. 24.
This FFS mode liquid crystal display device 190 includes an array substrate AR and a color filter substrate CF. In the array substrate AR, a plurality of scanning lines 194 and common lines 196 is provided in parallel on the surface of a first transparent substrate 192, and a plurality of signal lines 198 is provided in a direction crossing the scanning lines 194 and the common lines 196. A counter electrode (also referred to as a “common electrode”) 200 formed of a transparent material, such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), and connected to each of the common lines 196 so as to cover a region partitioned by each of the scanning lines 194 and each of the signal lines 198 is provided. A pixel electrode 206 formed of a transparent material such as ITO and having a plurality of slits 204 formed therein in a stripe shape is provided on the surface of the counter electrode 200 with an insulating film 202 interposed therebetween. The surfaces of the pixel electrode 206 and the plurality of slits 204 are covered by an alignment film 208.
A TFT functioning as a switching element is formed in the vicinity of an intersection of each of the scanning lines 194 and each of the signal lines 198. In this TFT, a semiconductor layer 210 is disposed on the surface of each of the scanning lines 194, a portion of each of the scanning lines 198 extends so as to cover a portion of the surface of the semiconductor layer 210 such that a source electrode S is configured, a portion of each of the scanning lines under the semiconductor layer 210 configures a gate electrode G, a conductive layer partially overlapping with a portion of the semiconductor layer 210 configures a drain electrode D, and this drain electrode D is connected to the pixel electrode 206.
In the color filter substrate CF, a color filter layer 214, an overcoat layer 216 and an alignment film 218 are provided on the surface of a second transparent substrate 212. The array substrate AR and the color filter substrate CF face each other such that the pixel electrode 206 and the counter electrode 200 of the array substrate AR and the color filter layer 214 of the color filter substrate CF face each other. Subsequently, liquid crystal LC is filled between the array substrate AR and the color filter substrate CF, and polarization plates 220 and 222 are arranged on the outsides of both substrates such that polarization directions thereof cross each other, thereby forming the FFS mode liquid crystal device 190.
In the FFS mode liquid crystal display device 190, if an electric field is generated between the pixel electrode 206 and the counter electrode 200, as shown in FIG. 25, this electric field is directed to the counter electrode 200 at both sides of the pixel electrode 206. Accordingly, the liquid present on the pixel electrode 206 as well as the liquid crystal present in the slits 204 may move.
However, in the IPS mode liquid crystal display device 150, it is difficult to twist liquid crystal molecules on the electrodes by the size of the electric field strength such that brightness of display deteriorates. In the FFS mode liquid crystal display device 190, it is difficult to twist liquid crystal molecules on the electrodes or between the electrodes by the size of the electric field strength such that brightness of display deteriorates.